It has always been challenging to fill polymeric materials in the iso-dense contact or via with less filling variation. It was also challenging to etch the dual damascene structures on top of via with various pitches of via hole present in the chip.
As shown in FIGS. 1A, 1B and 1C, bottom anti-reflective coating (BARC) 114; 124; 134 always unevenly fills via openings 116; 126; 136 of different pitches like 1:1 of FIG. 1A, 1:3 of FIG. 1B and 1:5 of FIG. 1C on the same wafer. It is noted that the via opening densities of FIGS. 1A, 1B and 1C may be on differing portions of the same wafer 111.
BARC has a tendency to fill to a greater degree in the iso-dense pattern vias 136 of FIG. 1C compared to dense pattern via openings 116 of FIG. 1A with the moderate density pattern vias 126 of FIG. 1B having BARC 124 filled via openings 126 falling between FIGS. 1C and 1A as shown. During the subsequent trench etching step of the dual damascene process, it is difficult to optimize the trench etch recipe due to uneven filling of the via openings 116; 126; 136 within the differing via opening densities FIGS. 1A, 1B and 1C of the wafer 111. Uneven BARC 114; 124; 134 filling always cause either over etch of the substrate 112; 122; 132 due to less BARC fill 114 in dense via openings 116 as shown in FIG. 1A or fence formation because of more BARC filling 134 in iso-dense via openings 136 as shown in FIG. 1C during trench etching. Both are undesirable for the ideal dual damascene process.
In the development of semiconductor industry, an improvement in operation speed of the device has always been a technology that all semiconductor manufacturers are competing. With a rapid development of an integrated circuit process, a resistance of a conductive line and a parasitic capacitance between the conductive lines are determined as two key factors among all factors for influencing the operation speed of the device. Accordingly, a metal layer having a low resistance, such as a copper layer can substitute for an aluminum layer used in the conventional method for reducing the resistance of the conductive line. A low dielectric constant (k) material, such as a low-k organic dielectric layer can substitute for a silicon oxide layer used in the conventional method for reducing the parasitic capacitance between the conductive lines.
Generally, a dual damascene technique is a metal interconnect process with a high reliability and low cost, while a material selection for the metal interconnect is not limited by etching process for the metal. Therefore, this technique is widely applied to the manufacture of the copper line to reduce the resistance of the conductive line, and to further improve the operation speed and quality of the IC device. As there is a demand for a high operation speed of the device, fabricating the dual damascene with the low-k material layer has been practiced in the metal interconnect process of the semiconductor industry. Dual damascene is a multi-level interconnection process in which, in addition to forming the grooves of single damascene, conductive via openings are also formed.
As shown in FIGS. 2A and 2B, the dual damascene process requires two masking steps. FIG. 2A illustrates that first, the via 144 pattern within a low-k material layer 142 formed over a substrate 140 is etched. FIG. 2B that second, the trench 146 pattern for the conductive lines are formed above the respective etched via 144′ pattern.
In the current practice of semiconductor manufacturing the liquid materials are most often deposited using either spin or spray coating methods employing a coater cup of a spin coater 150 as shown in FIG. 3 having a resist arm 152 and a supply nozzle (RRC nozzle) 154.
In a conventional spin coating process the semiconductor wafer to be processed is placed on a rotatable chuck and held in place by vacuum. The chuck is referred to by a variety of names, including spin chuck and vacuum chuck. The spin chuck has a diameter slightly less than that of the semiconductor wafer. The wafer is positioned on the chuck such that it is resting in a level horizontal plane with the inactive surface, designated as the bottom, in contact with the chuck and the opposite top surface is coated with the desired solution. In standard systems the chuck is powered and rotated by a motor.
In the spin coating process, the solution of specific quantity can be dispensed onto the wafer from a supply nozzle prior to spinning the wafer, which is referred to as static dispense or after the semiconductor wafer has been set in motion, which is termed dynamic dispense. In either case after the solution has been dispensed onto the top surface, the wafer is spun at a constant speed to establish a desired relatively uniform thickness of the solution across the wafer. Once the liquid layer acquires the relatively uniform and symmetrical profile, the remainder of the spin cycle allows the solvent in the solution to evaporate to produce a solid film on the wafer top surface.
After the solution is dispensed onto the wafer it is distributed uniformly over the surface largely as a result of the radial distribution of the liquid due to centrifugal and drag forces created by the spinning of the wafer. The solution deposited on the wafer goes through a number of stages during the spin process, primarily due to the fluid dynamics created by the spinning substrate.
In the conventional dual damascene process, to protect the via bottom during the trench etch (FIG. 2B), the most commonly used method is to completely fill the via opening 144 of FIG. 2A with BARC and than etch back BARC to give the equally height filled vias 144. This leads to extra steps and complexity in the process.
The resist coater shown in FIG. 3 may be used in the conventional coating method for coating a BARC film on semiconductor wafer.
FIG. 4 is a graph illustrating rotating speed (the y-axis) versus time (the x-axis) for a wafer in each step in the conventional coating method to fill the vias with BARC prior to the trench process to form the dual damascene structure opening. BARC having, for example, a relatively low viscosity on the order of 6 cp. is used for a BARC film coating. The wafer is held on the wafer chuck and the BARC is first dripped on a wafer from the resist supply nozzle, while rotating the wafer at a low rotational speed of about 650 rpm as at 162. The BARC is spread on the whole coating surface of the wafer for 2.5 seconds as at 162.
Next, the dripping of BARC is suspended, and the wafer is rotated for 20 seconds at a rotational speed of about 5500 rpm as at 164, so that a BARC film having a desired thickness, i.e. e.g., of 600 Å is formed.
Then, a rinse agent is sprayed from the cleaning nozzle for 10 to 20 seconds at a rotational speed of about 2000 as at 166, and the back surface edge of the wafer is cleaned. Thus, the coating step is terminated. Subsequently, the process proceeds to the baking steps, where the residual solution in the BARC is completely removed.
U.S. Pat. No. 6,251,487 B1 to Yonaha describes a method for coating a resist film.
U.S. Pat. No. 4,741,926 to White et al. describes a spin-coating procedure.
U.S. Pat. No. 6,319,821 B1 to Liu et al. describes a dual damascene process with BARC and via fill.
U.S. Pat. No. 6,042,999 to Lin et al. also describes a dual damascene process with BARC and via fill.